This Document Conventions Signals Symbols Mathematical Notation Functional Description Introduction Organization of the Functional Description Functional Overview Data Path VMEbus Interface Local Bus Interface Function Bus Request Modes Fair and Demand Modes VMEbus Request Levels Bus Release Modes Bus Clear Enabling Release On Request and Release When Done Ownership Timer Other Bus Release Mechanisms Local Memory Interrupt BI-Mode VMEbus Requester Local and System Reset VMEbus Interrupts Interrupt Generation BI-mode Effects Reset Effects Local Bus Interrupts Interrupt Enabling and Status Local Interrupt Level Mapping interrupt

Acknowledge Cycles Auto-Vectored Interrupts Vectored Interrupts BI-Mode Effects Reset Effects Syscon Determination IACK Daisy Chain Driver VMEbus Arbiter Arbitration Modes Arbitration Time-out Reset Effects Bus Timer System Clock Driver External Inputs External Status Off-Board Reset Input Reset Effects on Syscon Functions SCV64 as VME Slave Coupled Mode Interrupter Interrupt Handler System Controller Functions Data Path Decoupled Mode SCV64 as VME Master Coupled Mode Decoupled Mode DMA Transfers CPU Memory Map VME Slave Memory Map Automatic Base Address Programming Access Protection SCV64 as VME Master Address Translation Byte Lane Translation VMEbus Mastership RMW Cycles Termination of a Master Cycle with RETRY* SCV64 as VME Slave Address Translation Byte Lane Translation Local Bus Mastership DMA Transfers Master/Slave Deadlock Resolution Location Monitor Access Bus Busy Glitch BI-Mode Effects Bus Error Handling Local Bus Arbitration Local Arbiter Bypassed Local Arbiter Active Memory Mapping VMEbus Interface Local Bus Interface Local Cycles – Overview Cycle Initiation Data Transfer Cycle Termination Signals Bus Error Handling SCV64 as Local Slave SCV64 as Local Master Register Access Burst Cycles urst Reads Burst Writes Local Address Incrementation Read-Modify-Write Cycles Master/Slave Deadlock Resolution Deadlock Resolution in Decoupled Mode Location Monitor Access Reflected Cycles VSBbus Access BI-Mode Location Monitor and LMFIFO DMA Controller DMA Initialization Addressing and Data Transfer Modes Data Transfer Counts FILL Option No Release Option DMA Completion and Error Checking Resets Local Reset ystem Reset Resets, Clocks and Timers Power-up Reset Reset Effects on SCV64 Internal Resources Clocks Clocks Required Clocks Generated Timers Local Bus Timer Tick Timer Watchdog Timer VMEbus Timers Local IACK Cycle Decoding Auto SYSCON select Local Arbiter Bypass Automatic Base Address Programming Power-up Modes BI-Mode Auto-ID The Auto-ID Cycle Auto-ID Self Test Internal Delay Line Calibration Test and Diagnostic Modes Decoupled Write Diagnostics Loopback Diagnostics Loopback Mode DMA Loopback Interrupt Loopback JTAG Support Description of SCV64

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